1. Field of the Invention
This invention generally relates to electronic circuitry and, more particularly, to a pseudo single-phase flip-flop (PSP-FF) circuit.
2. Description of the Related Art
Terms:                true single-phase clocking (TSPC);        setup time (tsu);        clock-to-Q delay (tcq);        hold time (tiH);        data-to-Q delay (tDo).        
Master-slave, pulsed, and TSPC-based flip-flops are known in the art. None, with the exception of the last, can incorporate complex logic (logic operations typically associated with combinational logic circuits) so as to increase the amount of work accomplished in one period of the clock cycle.
FIG. 1 is a schematic depicting a positive edge-triggered TSPC flip-flop (prior art). The TSPC flip-flop (TSPC-FF) has one of the lower latencies (tDQ=tSU+tCQ), and more, it can incorporate complex logic, but suffers from a number of well-known structural problems which render it unsafe for large-scale use in commercial integrated circuits.
During the low phase of the clock, the flip-flop master is transparent. That is, changes at input D appear inverted on node mDb (the output). But since MN2, gated by the clock, is off, the transfer of mDb to the slave is blocked. DbMF is in pre-charge, and held at Vdd by MP2. Since DbMF is high, MP3, as well as the clock-gated MN3, is off. Q is in high impedance (floating) and holds state dynamically by the charge stored on its endemic capacitance and external load.
On the rising edge of the clock (CLK→Vdd), the master becomes opaque (the input is not transparent to the output) and enters “high-impedance”. MP1 turns off, cutting off “mDb” from Vdd. However, as the pull down of the master is not clocked, mDb is allowed to transition low. It should however, hold beyond the clock rising edge for a period of time (tH, D=0) sufficient for DbMF to fall.
As the master enters “high-impedance”, the slave becomes transparent. Pre-charger MP2 turns off, and MN2 and MN3 turn on. If mDb is low, DbMF remains at Vdd but floats. If mDb is high, DbMF monotonically falls but can float low if D→1 after tH, D=0 is satisfied.
In either case, the state of DbMF is inverted and transferred to the output Q. After a short time beyond the clock edge—characterized by (tH, D=0), subsequent changes at D do not change the flip-flop state (mDb is cut off from Vdd).
During the high phase of the clock, Q is driven, but mDb and DbMF are in high impedance and hold their levels dynamically. Thus, to ensure a robust operation, keepers must be placed on the mDb and DbMF nodes.
Once the clock falls (CLK→0), DbMF is driven to Vdd and the clock-gated MN3 is turned off, placing Q in high impedance. Its state is dynamically held by the stored charge on endemic capacitance and output load. Coupling to, and leakage at this node can disturb its state. As opposed to the internal nodes of mDb and DbMF, a regenerative keeper placed at Q does not ensure robust operation as the state node of the slave (Q) remains exposed to external noise. The aforementioned operational characteristics of the circuit prove it to be a positive edge-triggered flip-flop. Some examples are keepers are presented below. Generally, a keeper is understood to be a circuit that maintains a logic state until it is charged or drained by adjacent connected circuitry.
The absence of keepers on the mDb, DbMF, and Q nodes, as well as the exposure of the state node to output disturbance are problems associated with the TSPC-FF design. Further, the design is sensitive to clock slope and internal race issues. On the falling edge of the clock, as the flip-flop master becomes transparent, the slave is turning opaque. Two race conditions relating to this transition can occur. A race between master and slave occurs if D=0 when clock falls and the clock-gated MP1 turns on. mDb transitions high, activating MN1. Concurrently, MN2 is turning off. For a sufficiently low clock edge rate, both transistors in the MN1/MN2 pull-down stack are on briefly, potentially disturbing DbMF when it has a logical value of “1”.
An intra-slave race may occur if MP2 is large. That is, if DbMF pre-charges too quickly and activates MN4 before MN3 shuts off. A logical value of “1” at Q may be disturbed through the MN3/MN4 pull-down stack. Similarly, a sufficiently low clock slew may disturb the aforementioned level regardless of the size of MP2.
A tCQ imbalance may also occur between transitions. As DbMF is held at Vdd prior to the rising edge of the clock, there is a pronounced difference between tCQ 1→0 and tCQ 0→1 transitions. The latter must first discharge DbMF to ground. While the slower of the two transitions determines the latency of the flip-flop, the shorter tCQ places a more stringent limit on the minimum gate-delay budget between flip-flops so as to avoid race.
An output glitch may occur when data does not transition. Assume that D=0 in two consecutive cycles. On the rising edge of the first cycle, DbMF is discharged causing Q to transition to a logical “1”. When the clock falls, DbMF is driven back to Vdd and Q holds state. On the rising edge of the next cycle, MN2 and MN3 come on. DbMF starts to discharge, but since MN4, gated by DbMF, is initially on, Q begins to discharge. Once DbMF is below the trip-point of the final stage, Q is returned to Vdd. Thus, the output exhibits a low-going glitch: Q 1→0→1 for D=0. Although this glitch is non-destructive, it causes additional power dissipation for downstream logic.
The design also creates a large clock load. True to its name, true single-phase clocking is devised so that the raw clock drives all three stages of the flip-flop (MP1, MN2, MP2, MN3) thus imposing a large load on the clock.
Timing Performance Metrics: Flip-flop latency is characterized by the data-to-Q delay which is the sum of its setup time, tSU, to the rising clock edge and clock-to-Q delay, tCQ, measured from the rising edge, i.e. tDQ=tSU+tCQ. In the case of TSPC-FF, the 1→0 data transition produces the larger delay for both tSU and tCQ. tSU is determined by the delay through the MP0/MP1 stack (mDb→1) and tCQ comprises the discharge of DbMF through MN1/MN2 stack summed with MP3 driving the output high. Therefore, it can be said that the TSPC-FF latency is about 3 gate delays.
The maximum flip-flop hold time, tH, coupled with its minimum tCQ and clock skew, determines the minimum number of logic gates required between two flops to avoid hold time violation and race. The less positive the hold time, the easier it is for the logical effort to ensure a race-free operation. Maximum hold time for the TSPC-FF is the time required for the data to remain low after the rising edge of the clock so that mDb succeeds in discharging DbMF. This amounts to slightly larger than 1 gate delay.
It would be advantageous if a flip-flop design could be made faster than the TSPC flip-flop, and able to incorporate complex logic.